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november 2009 doc id 16523 rev 1 1/55 1 l99mc6 configurable 6-channel device features 3 independently self configuring high-/low-side channels 3 low-side channels r on =0.7 (typ) at t j = 25 c current limit of each output at min. 0.6 a pwm direct mode bulb mode with recovery mode led mode with slew rate control bridge mode with cr osscurrent protection spi interface for data communication temperature warning all outputs overtemperature protected all outputs short-circuit protected configurable open-load detection in off mode v cc supply voltage 3.0 v to 5.25 v very low current consumption in standby mode 5 a (typ) internal clamp diodes hs switches operate down to 3 v crank voltage applications relay driver led driver motor driver mirror adjustment description the l99mc6 ic is a highly flexible monolithic medium current output driver that incorporates 3 dedicated low-side outputs (channels 4 to 6) and 3 independently self configuring outputs (channels 1 to 3) that can be used as either low- side or high-side drivers in any combination. the l99mc6 can control inductive loads, incandescent bulbs or leds. the l99mc6 can be used in a half bridge configuration with crosscurrent protection. the channel 2 can be controlled directly via the in/pwm pin for pwm applications. the in/pwm signal can be applied to any other output. the integrated 16-bit standard serial peripheral interface (spi) controls all outputs and provides diagnostic information: normal operation, open- load in off-state, overcurrent, temperature warning, overtemperature. powersso-16 table 1. device summary package order codes part number (tube) part number (tape & reel) powersso-16 l99mc6-lf L99MC6TR-lf www.st.com
contents l99mc6 2/55 doc id 16523 rev 1 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 dual power supply: v s and v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.1 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4.1 direct input in/pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.2 temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . 14 2.4.3 open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.4 overload detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 led mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7 bulb mode (programmable soft start function to drive loads with higher inrush current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 19 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 spi electrical character istics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
l99mc6 contents doc id 16523 rev 1 3/55 7.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3 dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.4 spi timing parameter definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 functional description of the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1.1 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1.2 serial data input (sdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1.3 serial data output (sdo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1.4 chip select not (csn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.2 spi communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2.2 command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2.3 global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.3 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.4 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.5 read and clear status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.6 read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 spi control and status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1 ram memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2 rom memory map (access with oc0 and oc1 set to ?1?) . . . . . . . . . . . . 34 9.3 control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.3.1 channel configuration decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.3.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.4 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4.1 example 1:switch on channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4.2 example 2: bridge mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.4.3 example 3: open-load detection in off-state in bridge configuration . . . 40 10 maximum demagnetization energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11 application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.1 powersso-16 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
contents l99mc6 4/55 doc id 16523 rev 1 13 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.2 powersso-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.3 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 appendix a acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
l99mc6 list of tables doc id 16523 rev 1 5/55 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7. undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 9. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. dynamic characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12. command byte - general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 table 13. data byte - general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 14. command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 15. operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 16. global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 17. global status register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 18. command byte for write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 19. command byte for read mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 20. command byte for read and clear status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 21. command byte for read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 22. ram memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 23. rom memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 24. control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 25. control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 26. control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 27. status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 28. status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 29. channel configuration decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 30. register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 31. command byte - example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 32. data byte - example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 33. data byte description - example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 34. command byte 1 - example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 35. data byte 1 - example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 36. data byte description 1 - example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 37. command byte 2 - example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 38. data byte 2 - example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 39. data byte description 2 - example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 40. command byte 1 - example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 41. data byte 1 - example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 42. data byte description 1 - example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 43. command byte 2 - example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 44. data byte 2 - example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 45. data byte description 2 - example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 46. auto and mutual thermal resistance - footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 47. auto and mutual thermal resistance - 2 cm 2 of cu heatsink. . . . . . . . . . . . . . . . . . . . . . . . 48 table 48. auto and mutual thermal resistance - 8 cm 2 of cu heatsink. . . . . . . . . . . . . . . . . . . . . . . . 49
list of tables l99mc6 6/55 doc id 16523 rev 1 table 49. powersso-16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 50. acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 51. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
l99mc6 list of figures doc id 16523 rev 1 7/55 list of figures figure 1. application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. configuration diagram (top view) not in scale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. output voltage clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. example of bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. example of programmable soft start function for inductive loads and incandescent bulbs. 16 figure 8. serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9. serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10. output turn on/off delays and slew rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. clock polarity and clock phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 12. spi frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 13. indication of the global error flag on do when csn is low and sck is stable . . . . . . . . . . 31 figure 14. bridge mode drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 15. open-load in bridge mode drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 16. configurable switch hsd - maximum turn-off current versus inductance. . . . . . . . . . . . . . 42 figure 17. configurable switch lsd - maximum turn-off current versus inductance . . . . . . . . . . . . . . 43 figure 18. fixed lsd switch - maximum turn-off current versus inductance. . . . . . . . . . . . . . . . . . . . 44 figure 19. l99mc6 as driver for incandescent bulb, leds and high-side or low-side relays . . . . . . . 45 figure 20. l99mc6 as motor driver (for example, for mirror adjustment) . . . . . . . . . . . . . . . . . . . . . . 46 figure 21. l99mc6 as driver for unipolar stepper motor driver, relay and leds. . . . . . . . . . . . . . . . . 47 figure 22. powersso-16 pc board (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 23. powersso-16 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 24. powersso-16 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 25. powersso-16 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
introduction l99mc6 8/55 doc id 16523 rev 1 1 introduction 1.1 application diagram figure 1. application diagram di spi control logic gnd csn sck do v bat pwm / in driver and protections config. out1 ol driver and protections config. out2 ol driver and protections config. out3 ol driver and protections lsd out4 ol driver and protections lsd out5 ol driver and protections lsd out6 ol charge pump vreg microcontroller vcc m active reverse polarity protection
l99mc6 introduction doc id 16523 rev 1 9/55 1.2 block diagram and pin description figure 2. block diagram 0 di csn sck do vcc vcc in/pwm ol vold 1 ol =1 ol ol ol ol spi gnd drn1 src1 drn2 src2 drn3 src3 drn4 drn5 drn6 vold 2 vold 3 vold 4 vold 5 vold 6 vols 1 vols 2 vols 3 open load drain [out1] open load source [out1] short circuit [out1] on/off [out1] open load drain [out2] open load source [out2] short circuit [out2] on/off [out2] open load drain [out3] open load source [out3] short circuit [out3] on/off [out3] open load drain [out4] short circuit [out4] on/off [out4] open load drain [out5] short circuit [out5] on/off [out5] open load drain [out6] short circuit [out6] on/off [out6] control logic charge pump vcp vcc vcc vcc vdrive1 -3 vdrive1 -3 vdrive1-3 vdrive1 -3
introduction l99mc6 10/55 doc id 16523 rev 1 table 2. pin functions pin symbol function 1 / tab gnd ground : reference potential 6in/pwm in/pwm direct mode: direct input for channel 2. other chann els can be driven in pwm mode via spi. 8vcc logic voltage supply 3.3 v/5 v: for this input a ceramic capacitor as close as possible to gnd is recommended 3 src1 source of configurable channel 1 4 drn1 drain of self configurable channel 1, in hs mode also v s supply 5 drn2 drain of self configurable channel 2 15 src2 source of self configurable channel 2 12 drn3 drain of self configurable channel 3 13 src3 source of self configurable channel 3 2 drn4 drain of channel 4 16 drn5 drain of channel 5 14 drn6 drain of channel 6 11 di spi data in: the input requires cmos logic levels and receives serial data from the microcontroller. the data is a 16-bit control word and the most significant bit (msb, bit 7) is transferred first. 9do spi data out: the diagnosis data is available via the spi and this tristate-output. the output remains in tristate, if the chip is not selected by the input csn (csn = high). 7csn spi chip select not (active low): this input is low active and requires cmos logic levels. the serial data transfer between the l99mc6 and microcontroller is enabled by pulling the input csn to low-level. 10 sck spi serial clock input: this input controls the internal shift regi ster of the spi and requires cmos logic levels.
l99mc6 introduction doc id 16523 rev 1 11/55 figure 3. configuration diag ram (top view) not in scale gnd drn4 src1 drn1 drn2 pwm/in csn vcc drn5 src2 src3 drn3 di sck do drn6 1 2 3 4 5 7 8 6 16 15 14 13 12 8 9 11 the tab must be connected to gnd tab = gnd powersso-16
description l99mc6 12/55 doc id 16523 rev 1 2 description 2.1 dual power supply: v s and v cc the supply voltage v cc (3.3 v/5 v) supplies the whole device. in case of power-on (v cc increases from undervoltage to v por off = 2.7 v, typical) the circuit is initialized by an internally generated power-on reset (por). if the voltage v cc decreases under the minimum threshold (v por on = 2.4 v, typical), the outputs are switched-off (high- impedance) and the status registers are cleared (see figure 4 ). figure 4. power-on reset 2.1.1 channels the channels 1 to 3 are self configuring high-side or low-side n-channel mosfets. this flexibility allows the user to connect loads in high-side or low-side configuration in any combination. in order to provide low r dson values for high-side configured switches (channels 1 to 3), a charge pump (cp) to drive the internal gate voltage(s) is implemented. if the charge pump is activated (encp1 = 1, discp2 = 0, see section 9.3: control and status registers ), the internal charge-pump uses v s from the drain of channel 1, as its power source. otherwise v cc is used to drive all channels. the channels 4 to 6 are n-channel low-side drivers. the source of the respective mosfet are internally connected to the device gnd. caution: for any high-side configuration, channel 1 must be used as a high-side switch. if channel 1 is configured as low-side, the charge pump has to be deactivated to avoid charge pump current from the drain. caution: the charge pump may not be deactivated (see section 9.3: control and status registers ) if one of the channels is in high-side configuration, while a short-circuit from the source to the battery is present. if these conditions occur, the voltage of the shorted source is applied to the vcc pin. v por hyst. i c is disabled all status registers are cleared v por off v por on v cc
l99mc6 description doc id 16523 rev 1 13/55 2.2 standby mode the standby mode of the l99mc6 is activated by spi command (en bit of ctrl 0 reset to 0, see section 9.3.2: register description ). the inputs and outputs are switched-off. the status registers are cleared and the control registers are reset to their default values. in the standby mode the current consumption is 5 a (typical value). a spi command is needed to switch the l99mc6 in normal mode. 2.3 inductive loads each switch is built by a power dmos transistor. for low-side configured outputs an internal zener clamp from the drain to gate with a breakdown of 31 v minimum provides for fast turn- off of inductive loads. for high-side configured outputs, an internal zener clamp with a breakdown of -15 v maximum provides for fast turn-off of inductive loads ( figure 5 ). the maximum clamping energy is specified in chapter 10 . figure 5. output voltage clamping 2.4 diagnostic functions all diagnostic functions (overload, open-load, temperature warning and thermal shutdown) are internally filtered and the condition has to be valid for at least 32 s (open-load: typ. 400 s, respectively) before the corresponding status bit in the status registers are set. the filters are used to improve the noise immunity of the device. open-load and temperature warning function are intended for information purpose and do not change the state of the output drivers. on contrary, the overload and thermal shutdown condition disable the corresponding driver (overload) or all drivers (thermal shutdown), respectively. without setting the overcurrent recovery bit in the input data register to logic high, the microcontroller has to clear the overcurrent status bit to reactivate the corresponding driver. (all switches have a corresponding overcurrent recovery bit) if this bit is set, the device automatically switches-on the outputs again after a short recovery time. with this feature the device can drive loads with start-up currents higher than the overcurrent limits (that is inrush current of incandescent lamps, cold resistance of motors and heaters, figure 7 ). time low side configuration gnd drain clamp voltage (v drn_cl1-6) = 35v) v s output current drain voltage time high side configuration v s source voltage output current gnd source clamp voltage (v src_cl1-3) = -19v)
description l99mc6 14/55 doc id 16523 rev 1 2.4.1 direct input in/pwm the in/pwm input allows channel 2 to be enabled without the use of spi. the in/pwm pin is or-ed with the spi command bit. this pin can be left open if the channel 2 is controlled only via the spi. this input has an internal pull-down. the in/pwm signal can also be applied to any other switches by the activation of the pwm mode. this input is suited for non-indu ctive loads that are pulse widt h modulated. this allows pwm control without further use of the spi. 2.4.2 temperature warning and thermal shutdown if the junction temperature rises above t j tw a temperature warning flag is set and is detectable via the spi. if the junction temperature increases above the second threshold t jsd , the thermal shutdown bit is set and power dmos transistors of all output stages are switched-off to protect the device. temperature warning flag and thermal shutdown bits are latched. in order to reactivate the output stages, the junction temperature must decrease below t jsd- t jsdhys and the thermal shutdown bit has to be cleared by the microcontroller. 2.4.3 open-load detection in off-state the open-load detection monitors the load at each output stage in off mode. a current source of 150 a (i old1-6 , i ols 1-3 ) is connected between drain and source or gnd. an open-load failure is detected if the drain or source voltage reaches an internal v old/s (2.0 v) for at least 3 ms (t dol typ. ). the corresponding open-load bit is set in the status register. in led mode the open-load detection is disabled and the current source is switched-off, which avoids a turn-on of the leds in off-state. 2.4.4 overload detection in case of an overcurrent condition, a flag is set in the corresponding status register. if the overcurrent signal is valid for at least t isc = 32 s, the overcurrent flag is set and the corresponding driver is switched-off to reduce the power dissipation and to protect the integrated circuit. if the overcurrent recovery bit of the output is zero the microcontroller has to clear the status bit to reactivate the corresponding driver. 2.5 bridge mode the l99mc6 can be configured as bridge driver. up to three half bridges can be used. in bridge mode the device is crosscurrent protected by an internal delay time. if one driver (ls or hs) is turned-off the activation of the other driver of the same half bridge is automatically delayed by the crosscurrent protection time. afte r the crosscurrent protection time is expired the slew rate limited switch-off phase of the driver is changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. due to this behavior it is always guaranteed that the previously activated driver is totally turned-off before the opposite driver starts to conduct. due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs without external free-wheeling diodes.
l99mc6 description doc id 16523 rev 1 15/55 the following combination must be used: channel 1 + 4, channel 2 + 5, channel 3 + 6 ( figure 6 ). a v s voltage exceeding the low-side clamping voltage (v drn_cl1-6 ) , while the high one of the high-side drivers is turned on, may cause a destruction of the device. caution: in bridge mode using channels 2 and 5, the in/pwm pin has to be grounded. therefore pwm mode on other channels is not possible. figure 6. example of bridge configuration 2.6 led mode open-load detection in off-state can be deactivated to avoid the turn on of the leds by the current source (150 a typ.) when the channel is switched-off. moreover, it is possible to select a high slew rate to support pwm operations with small duty cycle (see section 9.3.1: channel configuration decoding ). control v dd 5v spi = 1 out1 out2 out3 out4 out5 out6 gnd in/pwm v s 12v m gnd sck csn do di m
description l99mc6 16/55 doc id 16523 rev 1 2.7 bulb mode (programmable soft start function to drive loads with higher inrush current) loads with start-up currents higher than the overcurrent limits (for example inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable soft start function (that is overcurrent recovery mode). each driver has a corresponding overcurrent recovery bit. if this bit is set, the device automatically switches-on the outputs again after a fixed recovery time. the pwm modulated current provides sufficient average current to power up the load (for example heat up the bulb) until the load reaches operating condition ( figure 6 ). the device itself cannot distinguish between a real overload and a non linear load like a light bulb. a real overload condition can only be qualified by time. as an example the microcontroller can switch-on light bulbs by setting the overcurrent recovery bit for the first 50 ms. after clearing the recovery bit, the output is automatically disabled if the overload condition still exits. figure 7. example of programmable soft start function for inductive loads and incandescent bulbs load current unlimited inrush current limited inrush current in overcurrent recovery mode with inductive load t load current unlimited inrush current limited inrush current in overcurrent recovery mode with incandescent bulb t
l99mc6 absolute maximum ratings doc id 16523 rev 1 17/55 3 absolute maximum ratings stressing the device above the rating listed in ta b l e 3 may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics? sure progra m and other relevant quality document. all maximum ratings are absolute ratings. leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit. table 3. absolute maximum ratings symbol parameter value unit v s (drn1 hs config) dc supply voltage -0.3 to 28 v single pulse t max < 400 ms in hs or ls configuration with r load min = 40 (1) 1. the device requires a minimum load impedance of 40 to sustain a load dump pulse of 40 v according to the iso 7637 pulse 5b. 40 v single pulse t max < 400 ms in bridge mode v drn_cl1-6 v v cc stabilized supply voltage, logic supply -0.3 to 5.5 v di, do, sck, csn, in digital input/output voltage -0.3 to v cc + 0.3 v drn 1-6 output current capability 1,65 a src 1-3 output current capability 1,65 a gnd current capability 3,30 a t j operating junction temperature -40 to 150 c
esd protection l99mc6 18/55 doc id 16523 rev 1 4 esd protection table 4. esd protection parameter value unit all pins 2 (1) 1. hbm according to mil 883c, method 3015.7 or eia/jesd22-a114-a kv output pins: drn1 ? drn6; src1, src3, src5 4 (2) 2. hbm with all unzapped pins grounded kv machine model (cdf-aec-q100-03 rev. f) 200 v charged device model (cdf-aec-q100-011 rev. f) 1500 v
l99mc6 thermal data doc id 16523 rev 1 19/55 5 thermal data 5.1 temperature warnin g and thermal shutdown for additional information, please refer to chapter 12: package and pcb thermal data . table 5. temperature warning and thermal shutdown item symbol parameter min. typ. max. unit 5.2.1 t jtw on temperature warning threshold junction temperature t j increasing 150 c 5.2.2 t jtw off temperature warning threshold junction temperature t j decreasing 130 c 5.2.3 t jtw hys temperature warning hysteresis - 5 k 5.2.4 t jsd on thermal shutdown threshold junction temperature t j increasing 170 c 5.2.5 t jsd off thermal shutdown threshold junction temperature t j decreasing 150 c 5.2.6 t jsd hys thermal shutdown hysteresis - 5 k
electrical characteristics l99mc6 20/55 doc id 16523 rev 1 6 electrical characteristics v s =6v to16v, v cc = 3.0 v to 5.3 v, t j = -40 c to 150 c, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6.1 supply 6.2 undervoltage detection table 6. supply item symbol parameter test condition min. typ. max. unit 6.1.1 v s operating supply voltage range 628v 6.1.2 i s v s dc supply current v s =13v, v cc =5.0v active mode drn1 = v s outputs floating 1.5 2.0 ma 6.1.3 i vs v s quiescent supply current v s =13v, v cc =5v standby mode drn1 = v s t te s t = -40 c, 25 c outputs floating 310 a t te s t =130 c 6 20 a 6.1.4 v cc operating supply voltage range 3.0 5.3 v 6.1.5 i cc v cc dc supply current v s =13v, v cc =5.0v active mode 1.3 2 ma 6.1.6 v cc quiescent supply current v s =13v, v cc =5.0v csn = v cc standby mode outputs floating 520a table 7. undervoltage detection item symbol parameter test condition min. typ. max. unit 6.2.1 v por off power-on reset threshold v cc increasing 3.0 v 6.2.2 v por on power-on reset threshold v cc decreasing 2.2 v 6.2.3 v por hyst power-on reset hysteresis v por off - v por on 0.3 v
l99mc6 electrical characteristics doc id 16523 rev 1 21/55 6.3 channels table 8. channels item symbol parameter test condition min. typ. max. unit 6.3.1 r on swi1-3 on resistance drain to source in hs configuration v s =13.5 v, t j =25c, cp on, i load =250ma - 700 900 m v s =13.5 v, t j =125c, cp on, i load =250ma - 1100 1500 m v s =6.0v t j =25c, cp on, i load =125ma - 700 900 m v s =6.0v, t j =125c, cp on, i load =125ma - 1100 1500 m v s =4.5v t j =25c, cp on, i load =125ma - 800 1500 m v s =4.5v, t j =125c, cp on, load = 125 ma - 1300 2000 m v s =3v, t j =25c, cp on, i load =125ma - 1600 2600 m 6.3.2 r on swi1-6 on resistance drain to source or gnd, in ls configuration v cc =5.0 v, t j =25c, load = 250 ma - 750 1000 m v cc = 5.0 v, t j =125c, i load =250ma - 1100 1500 m v cc = 3.3 v, t j =25c, i load =250ma - 900 1250 m v cc = 3.3 v, t j =125c, i load =250ma - 1400 1800 m 6.3.3 i sc1-6 overcurrent protection channel s 1 to 3 0.7 1.0 1.4 a channels 4 to 6 0.6 0.8 1.0 a 6.3.4 t d on1-6 output delay time, switch-on v s = 13.5 v, v cc = 5.0 v - 50 100 s 6.3.5 t d off1-6 output delay time, switch-off v s = 13.5 v, v cc = 5.0 v - 50 100 s 6.3.6 t d onled1-6 output delay time, switch-on led v s = 13.5 v, v cc =5.0v - 15 40 s 6.3.7 t doffled1-6 output delay time, switch-off led v s = 13.5 v, v cc =5.0v - 15 40 s 6.3.8 t dhl crosscurrent protection time only in bridge mode - 200 500 s 6.3.9 i qld switched-off output current drn 1-6 v drn2-6 =v s , led mode, cp off 0-5a v drn1 -20 a
electrical characteristics l99mc6 22/55 doc id 16523 rev 1 6.3.10 i qls switched-off output current src 1-3 v src1-3 =gnd, led mode --15-25a 6.3.11 v old1-6 drain open-load detection voltage on drain 1,1 2,0 2,5 v 6.3.12 i old1-6 open-load detection current on drain @ v old 80 190 280 a 6.3.13 v ols1-3 source open-load detection voltage on source 1,1 2,0 2,5 v 6.3.14 i ols1-3 open-load detection current on source @ v ols -80 -190 -280 a 6.3.15 t dol minimum duration of open- load condition to set the status bit guaranteed by design 2 3 4 ms 6.3.16 t isc minimum duration of overcurrent condition to switch-off the driver guaranteed by design 10 - 100 s 6.3.17 dv out1 /dt slew rate of channel 1 to 6 v s =13.5v, v cc =5.0v i load =54 0.1 0.25 0.4 v/s 6.3.18 dv out1led /dt slew rate of channel 1 to 6 in led mode v s =13.5v, v cc =5.0v i load =54 0.5 1.25 2.0 v/s 6.3.19 v drn_cl1-6 drain clamp voltage (low-side) source = gnd i load =0.25a 31 35 39 v 6.3.20 v src_cl1-3 source clamp voltage (high-side) drain = v s , i load = 0.25 a -22 -19 -15 v standby -22 10 -1,5 v table 8. channels (continued) item symbol parameter test condition min. typ. max. unit
l99mc6 spi electrical characteristics doc id 16523 rev 1 23/55 7 spi electrical characteristics v s =6v to16v, v cc = 3.0 v to 5.3 v, t j = -40 c to 150 c, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin 7.1 dc characteristics 7.2 ac characteristics table 9. dc characteristics symbol parameter test condition min typ max unit di, sck, csn, pwm v il low-level input voltage - 0.3v dd v v ih high-level input voltage - 0.7v dd v r csn in pull-up resistor at input csn - 20 50 80 k r clk in pull-down resistor at input clk - 20 50 80 k r di in pull-down resistor at input di - 20 50 80 k do v ol low-level output voltage i out = 5 ma 0.3v dd v v oh high-level output voltage i out = 5 ma 0.7v dd v table 10. ac characteristics symbol parameter test condition min typ max unit di, do, sck, csn c out output capacitance (do) v out = 0 to 5 v - - 10 pf c in input capacitance (di) v in = 0 to 5 v - - 10 pf input capacitance (other pins) v in = 0 to 5 v - - 10 pf
spi electrical characteristics l99mc6 24/55 doc id 16523 rev 1 7.3 dynamic characteristics table 11. dynamic characteristic symbol parameter test condition min typ max unit f c clock frequency - - - 1 mhz t scsn csn low setup time see figure 8 120 - - ns t hcsn csn high setup time see figure 8 1- - s t csnqv csn falling until do valid - 5 130 250 ns t csnqt csn rising until do tristate - 150 650 1000 ns t ssck sck setup time before csn rising - 200 - - ns t ssdi data in setup time see figure 8 20 - - ns t chdx data hold setup time see figure 8 30 - - ns t hsck sck high time see figure 8 115 - - ns t lsck sck low time see figure 8 115 - - ns t sckqv clock high to output valid c out = 100 pf - 150 - ns t qlqh output rise time c out = 100 pf - 110 - ns t qhql output fall time c out = 100 pf - 110 - ns t endotrih do enable time from tristate to high-level c out = 100 pf, i out = -1 ma, pull-down load to gnd - 100 250 ns t endotril do enable time from tristate to low-level c out = 100 pf, i out =1 ma, pull-up load to v cc - 100 250 ns t disdohtri do disable time from high-level to tristate c out = 100 pf, i out = -4 ma, pull-down load to gnd - 625 720 ns t disdoltri do disable time from low-level to tristate c out = 100 pf, i out =4ma, pull-up load to v cc - 540 620 ns
l99mc6 spi electrical characteristics doc id 16523 rev 1 25/55 7.4 spi timing parameter definition figure 8. serial input timing figure 9. serial input timing csn sdo data out t csnqt t sckqv sck data out t hsck t lsck t scsn t hcsn data in data in t ssdi sdi t csnqv t ssck t disdo h tri t end o tri h t disdo l tri t end o tri l csn sdo pull-up load to vcc c l =100pf sdo pull-down load to gnd c l =100pf
spi electrical characteristics l99mc6 26/55 doc id 16523 rev 1 figure 10. output turn on/off delays and slew rates 50% 90% 10% v inipwm v dd gnd gnd gnd lowside high side v source x v drain x 20% 80% 20% t don1-6 80% dvout1x/dt 50% 90% v in/pwm v dd gnd gnd lowside high side v source x v drain x 20% 10% t doff1-6 dvout1x/dt 90% 80% 20%
l99mc6 functional description of the spi doc id 16523 rev 1 27/55 8 functional description of the spi 8.1 signal description 8.1.1 serial clock (sck) this input signal provides the timing of the seri al interface. data present at serial data input (sdi) is latched on the rising edge of serial clock (sck). data on serial data output (sdo) is shifted out at the falling edge of serial clock (see figure 11 ). the spi can be driven by a microcontroller with its spi peripherals running in following mode: cpol = 0 and cpha = 0 (see figure 11 ). 8.1.2 serial data input (sdi) this input is used to transfer data serially into the device. it receives the data to be written. values are latched on the rising edge of serial clock (sck). 8.1.3 serial data output (sdo) this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (sck). do also reflects the status of the (, bit 7) while csn is low and no clock signal is present 8.1.4 chip select not (csn) when this input signal is high, the device is de selected and serial data output (sdo) is high- impedance. driving this input low enables the communication. the communication must start and stop on a low-level of serial clock (sck). figure 11. clock polarity and clock phase
functional description of the spi l99mc6 28/55 doc id 16523 rev 1 figure 12. spi frame structure csn sdo sdi command byte (8 bit) spi-frame structure global status byte (8 bit) data (8, 16 or 24 bit) msb msb lsb lsb data (previous content of register) write operation csn sdo sdi command byte (8 bit) global status byte (8 bit) don?t care (8, 16 or 24 bit) msb msb lsb lsb data (8, 16 or 24 bit) read operation msb lsb msb lsb
l99mc6 functional description of the spi doc id 16523 rev 1 29/55 8.2 spi communication flow 8.2.1 general description the proposed spi communication is based on a standard spi interface structure using csn (chip select not), sdi (serial data in), sdo (serial data out/error) and sck (serial clock) signal lines. at the beginning of each communication the master reads the register (rom address 3eh) of the slave device. this 8-bit register indicates the spi frame length (16 bit for the l99mc6) and the av ailability of addi tional features. each communication frame consists of an instruction byte which is followed by 1 data byte (see figure 12 ). the data returned on sdo within the same frame always starts with the register. it provides general status information about the device. it is followed by 1 byte (that is ?in-frame-response?, see figure 12 ). for write cycles the register is followed by the previous content of the addressed register. for read cycles the register is followed by the content of the addressed register. 8.2.2 command byte each communication frame starts with a command byte. it consists of an operating code which specifies the type of operation (, , , ) and a 6-bit address. table 12. command byte - general description msb lsb operating code address oc1 oc0 a5 a4 a3 a2 a1 a0 table 13. data byte - general description msb lsb bit7 bit6 bit5 bi4 bit3 bit2 bit1 bit0 table 14. command byte msb lsb operating code address oc1 oc0 a5 a4 a3 a2 a1 a0
functional description of the spi l99mc6 30/55 doc id 16523 rev 1 operating code definition the and operations allow access to the ram of the device, that is write to control registers or read status information. a operation addressed to a device specific status register reads back and subsequently clear this status register. a operation with address 3fh clears all status registers at a time. a operation addressed to an unused ram address or configuration register address is identical to a operation (in case of unused ram address, the second byte is equal to 00h). allows access to the rom area which contains device related information such as the produ ct family, product name, silic on version and register width. 8.2.3 global status register table 15. operating code definition oc1 oc0 meaning 0 0 0 1 1 0 1 1 table 16. global status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 global error flag (gef) communication error chip reset tsd chip overload temperature warning open-load detected overcurrent detected unused table 17. global status register description bit description polarity comment 0 unused active high always returns ?0? 1 overcurrent detected active high set by any overcurrent event 2 open-load detected active high set by any open-load event 3 temperature warning active high - 4 thermal shutdown / chip overload active high - 5 chip reset active low activated by all internal reset events that change device state or configuration registers (for example software reset, v cc undervoltage, etc.). the bit is cleared after a valid communication with any register. this bit is initially ?0? and is set to ?1? by a valid spi communication
l99mc6 functional description of the spi doc id 16523 rev 1 31/55 the is generated by an or-combination of all failure events of the device (that is < global status register>, [0:6] ). figure 13. indication of the global error flag on do when csn is low and sck is stable 1. the last transferred spi command is still valid in the input sh ift register. if sck is stable (high or low) during a csn low pulse, at the rising edge of csn the last transferred spi command is still valid in the input sh ift register and is repeated. therefore, it is recommended to send a complete spi frame to monitor the status of the l99mc6. writing to the selected data input register is only enabled if exactly one frame length is transmitted within one communication frame (that is csn low). if more or less clock pulses are counted within one frame, the complete frame is ignored and a spi frame error is signaled in the global status register. this safety function is implemented to avoid an unwanted activation of output stages by a wrong communication frame. 6 communication error active high bit is set if the number of clock cycles during csn = low does not matc h with the specified frame width or if an invalid bus condition is detected (di always 1). di always 0 automatically leads to clearing the enable bit in ctrl0 and is not signaled as communication error. 7 global error flag active high logic or combination of all failures in the . table 17. global status register description (continued) bit description polarity comment
functional description of the spi l99mc6 32/55 doc id 16523 rev 1 for read operations, the bit in the is set, but the register to be read is still transferred to the do pin. if the number of clock cycles is smaller than the frame width, the data at do is truncated. if the number of clock cycles is larger than the frame width, the data at do is filled with ?0? bits. due to this safety functionality a daisy chaining of spi is not possible. instead, a parallel operation of the spi bus by controlling th e csn signal of the connected ics is recommended. note: if the frame width is greater than 16 bits, initial read of using a 16-bit communication sets the of the register. a subsequent correct length transaction is necessary to correct this bit. 8.3 write operation oc0, oc1: operating code (00 for ?write? mode) the write operation starts with a command byte followed by 1 data byte. for write cycles the register is followed by the previous content of the addressed register. the ram memory area consists of 8-bit regist ers. all unused ram addresses are read as ?0?. failures are indicated by activating the corresponding bit of the register. note: the register definition for ram address 00h is device specific. a register value of all 0 causes a device reset (interpreted as ?data-in short to gnd?). 8.4 read operation oc0, oc1: operating c ode (01 for ?read? mode) the read operation starts with a command byte followed by 1 data byte. the content of the data byte is ?do not care?. the content of the addressed register is shifted out at sdo within the same frame (?in-frame response?). the returned data byte represents the content of the register to be read. failures are indicated by activating the corresponding bit of the register. table 18. command byte for write mode msb lsb operating code address 0 0 a5 a4 a3 a2 a1 a0 table 19. command byte for read mode msb lsb operating code address 0 1 a5 a4 a3 a2 a1 a0
l99mc6 functional description of the spi doc id 16523 rev 1 33/55 8.5 read and clear status operation oc0, oc1: operating code (10 for ?read and clear status? mode) the ?read and clear status? operation starts with a command byte followed by 1 data byte. the content of the data byte is ?do not care?. the content of the addressed status register is transferred to sdo within the same frame (?in-frame response?) and is subsequently cleared. a operation with address 3fh clears all status registers simultaneously. a operation addressed to an unused ram address or to the configuration register (3fh) is identical to a operation (in case of unused ram address, the second byte is equal to 00h). the returned data byte represents the content of the register to be read. failures are indicated by activating the corresponding bit of the register. 8.6 read device information oc0, oc1: operating code (11 fo r ?read device information? mode) the device information is stored at the rom. in the rom memory area, the first 8 bits are used. all unused rom addresses is read as ?0?. note: rom address 3fh is unused. an attempt to access this address is recognized as a communication line error (?data-in stuck to v cc ?) and the standby mode is automatically entered (all internal registers are cleared). table 20. command byte for read and clear status operation msb lsb operating code address 1 0 a5 a4 a3 a2 a1 a0 table 21. command byte for read device information msb lsb operating code address 1 1 a5 a4 a3 a2 a1 a0
spi control and status register l99mc6 34/55 doc id 16523 rev 1 9 spi control and status register 9.1 ram memory map 9.2 rom memory map (access with oc0 and oc1 set to ?1?) 9.3 control and status registers table 22. ram memory map address name access content 00h ctrl 0 read/write global enable, channels 3 and 6 control register 01h ctrl 1 read/write cp, channels 2 and 5 control register 02h ctrl 2 read/write cp, channels 1 and 4 control register 03h unused - - 04h stat 0 read only open-load / thermal status register 05h stat 1 read only overcurrent / thermal status register table 23. rom memory map address name access content 00h id header read only 42h (device class assp, 2 additi onal information bytes) 01h product id read only 06h 02h category / version read only 18h (multi channel driver, last 3 lsb = 0: engineering samples) 3eh spi-frame id read only 01h (no burst mode, no watchdog, 16 bit frame spi) table 24. control register 0 adress access data byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 global enable, channel 3&6 control 00h r/w en ch6 [2] ch6 [1] ch6 [0] bridge 3&6 ch3 [2] ch3 [1] ch3 [0] default 00000000
l99mc6 spi control and status register doc id 16523 rev 1 35/55 table 25. control register 1 adress access data byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 channel 2&5 control 01h r/w encp ch5 [2] ch5 [1] ch5 [0] bridge 2&5 ch2 [2] ch2 [1] ch2 [0] default 10000000 table 26. control register 2 adress access data byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 channel 1&4 control 02h r/w discp ch4 [2] ch4 [1] ch4 [0] bridge 1&4 ch1 [2] ch1 [1] ch1 [0] default 00000000 table 27. status register 0 adress access data byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 open-load, thermal status 04h r tsd twarn ol ch6 ol ch5 ol ch4 ol ch3 ol ch2 ol ch1 table 28. status register 1 adress access data byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 overcurrent, thermal status 05h r tsd twarn oc ch6 oc ch5 oc ch4 oc ch3 oc ch2 oc ch1
spi control and status register l99mc6 36/55 doc id 16523 rev 1 9.3.1 channel conf iguration decoding 9.3.2 register description table 29. channel configuration decoding chx [2] chx [1] chx [0] chx pwm mode overcurrent recovery slew rate open-load detection 000off (1) no - high off 111off (1) no - low on 001 on no nohigh - 010 on no nolow - 011 on noyeslow - 101in/pwm (2) yes no high off 110in/pwm (2) ye s n o l o w o n 1. the state of the channel 2 is according to the in/pwm signal 2. the output state is according to the in/pwm signal, note that bridge mode and pwm mode may not be activated at the same time for channels 2 and 5. table 30. register description (1) name comment en global device enable bit. if this bit is reset, the device goes in standby mode. chx [2:0] channel output configuration (see figure 29 ). note that channel 2 is directly driven by the external in/pwm pin and thus can not be configured independently from the pwm configuration of other channels. bridge activate bridge mode between channels 3 and 6, channels 2 and 5, channels 1 and 4. any polarity change is delayed by masking time of cross conduction protection if wrong spi commands try to turn on the ch annels 3 and 6, channels 2 and 5, channels 1 and 4 simultaneously, the high-side (channels 3, 2, 1) has the priority whereas channels 6, 5, 4 is (or stay) deactivated. encp this bit is preset to ?1? at startup. to deacti vate the internal charge pump encp has to be reset together with setting discp (ctrl 2). this mechanism avoids unwanted charge pump deactivation after an undetected communication error. it is recommended to check the state of the char ge pump deactivation bits at every access of ctrl 1 and ctrl 2. discp this bit is reset to ?0? at startup. to deactivate the internal charge pump discp has to be set together with resetting encp (ctrl 1) tsd overtemperature detected: all the drivers are shutdown twarn overtemperature warning level detected, information only ol [6:1] open-load error detected, information only oc [6:1] overcurrent error detected, drivers are deactivat ed and re-enabled cyclically when bulb mode is configured. note: in order to detect a real over load condition, the application software must make sure, that the corresponding oc bit remains cleared after a maximum heat up time of the load. 1. every output stage is protected against overtemperature and overcurrent. while st ill configured as on, the output stage can be deactivated by the correspondi ng error bits in the status registers. in or der to reactivate the drivers, the status registers have to be cleared by a specific spi command.
l99mc6 spi control and status register doc id 16523 rev 1 37/55 9.4 examples 9.4.1 example 1:switch on channel 1 it is assumed that the charge pump is already activated (encp1 = 1 and discp2 = 0, por default) from ta bl e 3 1 and ta bl e 3 2 follow that the value 01h is written at ram address 02h (control register 2). ta bl e 3 3 describe more in detail the data byte structure. hereafter the actions linked to each value of bit or group of bits: discp = 0 : charge pump stays activated ch4[2:0] = 000b : channel 4 is off, open-load detection in off-state disabled bridge_1&4 = 0 : bridge mode disabled ch4[2:0] = 001b : channel 1 is on, high slew rate, pwm not activated, overcurrent recovery deactivated. table 31. command byte - example 1 msb lsb operating code address 00000010 table 32. data byte - example 1 msb lsb 0 0 000 0 0 1 table 33. data byte description - example 1 discp ch4 [2] ch4 [1] ch4 [0] bridge 1&4 ch1 [2] ch1 [1] ch1 [0] 00000001
spi control and status register l99mc6 38/55 doc id 16523 rev 1 9.4.2 example 2: bridge mode configuration from ta b l e 3 4 and ta b l e 3 5 follow that the value a8h is written at ram address 01h (control register 1). ta bl e 3 6 describe more in detail the data byte structure. hereafter the actions linked to each value of bit or group of bits: encp = 1 : charge pump stays activated ch5[2:0] = 010b : channel 5 is on, pwm disabled, overcurrent recovery mode disabled, low slew rate bridge_2&5 = 1 : bridge mode for channel 2 and channel 5 activated ch2[2:0] = 000b : channel 2 is off, open-load detection in off-state disabled from ta b l e 3 7 and ta b l e 3 8 follow that the value 0ah is written at ram address 02h (control register 2). ta bl e 3 9 describe more in detail the data byte structure. table 34. command byte 1 - example 2 msb lsb operating code address 00000001 table 35. data byte 1 - example 2 msb lsb 1 0 101 0 0 0 table 36. data byte description 1 - example 2 encp ch5 [2] ch5 [1] ch5 [0] bridge 2&5 ch2 [2] ch2 [1] ch2 [0] 10101000 table 37. command byte 2 - example 2 msb lsb operating code address 00000010 table 38. data byte 2 - example 2 msb lsb 0 0 001 0 1 0
l99mc6 spi control and status register doc id 16523 rev 1 39/55 hereafter the actions linked to each value of bit or group of bits: discp = 0 : charge pump stays activated ch4[2:0] = 000b : channel 4 is off, open-load detection in off-state disabled bridge_1&4 = 1 : bridge mode for channel 1 and channel 4 activated ch4[2:0] = 010b : channel 1 is on, pwm disabled, overcurrent recovery mode disabled, low slew rate figure 14. bridge mode drawing table 39. data byte description 2 - example 2 discp ch4 [2] ch4 [1] ch4 [0] bridge 1&4 ch1 [2] ch1 [1] ch1 [0] 00001010 m vs ch4 off ch1 on ch 2 off ch 5 on
spi control and status register l99mc6 40/55 doc id 16523 rev 1 9.4.3 example 3: open-load detection in off-state in brid ge configuration from ta b l e 4 0 and ta b l e 4 1 follow that the value f8h is written at ram address 01h (control register 1). ta bl e 4 2 describe more in detail the data byte structure. hereafter the actions linked to each value of bit or group of bits: encp = 1 : charge pump stays activated ch5[2:0] = 111b : channel 5 is off, open-load detection in off-state enabled bridge_2&5 = 1 : bridge mode for channel 2 and channel 5 activated ch2[2:0] = 000b : channel 2 is off, open-load detection in off-state disabled from ta b l e 4 3 and ta b l e 4 4 follow that the value 0ah is written at ram address 02h (control register 2). ta bl e 4 5 describe more in detail the data byte structure. table 40. command byte 1 - example 3 msb lsb operating code address 00000001 table 41. data byte 1 - example 3 msb lsb 1 1 111 0 0 0 table 42. data byte description 1 - example 3 encp ch5 [2] ch5 [1] ch5 [0] bridge 2&5 ch2 [2] ch2 [1] ch2 [0] 11111000 table 43. command byte 2 - example 3 msb lsb operating code address 00000010 table 44. data byte 2 - example 3 msb lsb 0 0 001 0 1 0
l99mc6 spi control and status register doc id 16523 rev 1 41/55 hereafter the actions linked to each value of bit or group of bits: discp = 0 : charge pump stays activated ch4[2:0] = 000b : channel 4 is off, open-load detection in off-state disabled bridge_1&4 = 1 : bridge mode for channel 1 and channel 4 activated ch1[2:0] = 010b : channel 1 is on, pwm disabled, overcurrent recovery mode disabled, low slew rate figure 15. open-load in bridge mode drawing there are two operating conditions: case 1: the motor is connected, drain of channel 5 is pulled up by channel 1 (on) through the motor, then no open-load detected on channel 5 case 2 : the motor is not connected and the drain voltage of channel 5 is below the open-load threshold, then open-load detected on channel 5 table 45. data byte description 2 - example 3 discp ch4 [2] ch4 [1] ch4 [0] bridge 1&4 ch1 [2] ch1 [1] ch1 [0] 00001010 m vs ch4 off ol detection off ch1 on ol detection off ch2 off ol detection off ch5 off ol detection on
maximum demagnetization energy l99mc6 42/55 doc id 16523 rev 1 10 maximum demagnetization energy figure 16. configurable switch hsd - maximum turn-off current versus inductance a : single pulse, t j = 150 c b : repetitive pulse, t j = 100 c c : repetitive pulse, t j = 125 c 0.1 1 100 1000 l (mh) i (a) a b c
l99mc6 maximum demagnetization energy doc id 16523 rev 1 43/55 figure 17. configurable switch lsd - maximum turn-off current versus inductance 0.1 1 100 1000 l (mh) i (a) a b c a : single pulse, t j = 150 c b : repetitive pulse, t j = 100 c c : repetitive pulse, t j = 125 c
maximum demagnetization energy l99mc6 44/55 doc id 16523 rev 1 figure 18. fixed lsd switch - maximum turn-off current versus inductance 0.1 1 100 1000 l (mh) i (a) a : single pulse, t j = 150 c b : repetitive pulse, t j = 100 c c : repetitive pulse, t j = 125 c a b c
l99mc6 application examples doc id 16523 rev 1 45/55 11 application examples figure 19. l99mc6 as driver for incandescent bulb, leds and high-side or low-side relays control v dd 5v spi = 1 out1 out2 out3 out4 out5 out6 gnd in/pwm v s 12v sck csn do di
application examples l99mc6 46/55 doc id 16523 rev 1 figure 20. l99mc6 as motor driver (f or example, for mirror adjustment) control v dd 5v spi = 1 out1 out2 out3 out4 out5 out6 gnd in/pwm v s 12v m gnd sck csn do di m
l99mc6 application examples doc id 16523 rev 1 47/55 figure 21. l99mc6 as driver for unipolar stepper motor driver, relay and leds control v dd 5v spi out1 out2 out3 out4 out5 out6 gnd in/pwm v s 12v sck csn do di sm = 1
package and pcb thermal data l99mc6 48/55 doc id 16523 rev 1 12 package and pcb thermal data 12.1 powersso-16 thermal data figure 22. powersso-16 pc board (1) 1. layout condition of thermal resistance meas urements (pcb: double layer, thermal vias, fr4 area = 77 mm x 86 mm, pcb thickness =1.6 mm, cu thickness = 70 m (front and back side) thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, cu thickness on vias 25 m, footprint dimension 2.5 mm x 4.2 mm ). table 46. auto and mutual thermal resistance - footprint hsd 1 hsd 2 hsd 3 lsd 4 lsd 5 lsd 6 hsd 1 89.57 85.83 84.41 88.89 87.06 85.84 hsd 2 85.83 89.57 84.41 87.06 88.89 87.06 hsd 3 84.41 84.41 89.57 85.84 87.06 88.89 lsd 4 88.89 87.06 85.84 93.58 90.54 89.08 lsd 5 87.06 88.89 87.06 90.54 93.58 90.54 lsd 5 85.84 87.06 88.89 89.08 90.54 93.58 table 47. auto and mutual thermal resistance - 2 cm 2 of cu heatsink hsd 1 hsd 2 hsd 3 lsd 4 lsd 5 lsd 6 hsd 1 59.96 55.06 54.23 58.25 56.08 54.71 hsd 2 55.06 59.96 54.23 56.08 58.25 56.08 hsd 3 54.23 54.23 59.96 54.71 56.08 58.25 lsd 4 58.25 56.08 54.71 61.80 60.37 59.45 lsd 5 56.08 58.25 56.08 60.37 61.80 60.37 lsd 5 54.71 56.08 58.25 59.45 60.37 61.80 .
l99mc6 package and pcb thermal data doc id 16523 rev 1 49/55 equation 1 represents t j-amb calculation of a full loaded device for the hsd1 junction. equation 1 table 48. auto and mutual thermal resistance - 8 cm 2 of cu heatsink hsd 1 hsd 2 hsd 3 lsd 4 lsd 5 lsd 6 hsd 1 46.51 43.16 41.49 45.19 43.06 42.08 hsd 2 43.16 46.51 41.49 43.06 45.19 43.06 hsd 3 41.49 41.49 46.51 42.08 43.06 45.19 lsd 4 45.19 43.06 42.08 47.19 46.31 45.19 lsd 5 43.06 45.19 43.06 46.31 47.19 46.31 lsd 5 42.08 43.06 45.19 45.19 46.31 47.19 6 6 1 5 5 1 4 4 1 3 3 1 2 2 1 1 1 1 lsd lsd , hsd lsd lsd , hsd lsd lsd , hsd hsd hsd , hsd hsd hsd , hsd hsd hsd hsd pd rth pd rth pd rth pd rth pd rth pd rth t ? + ? + ? + + ? + ? + ? =
package and packing information l99mc6 50/55 doc id 16523 rev 1 13 package and packing information 13.1 ecopack ? in order to meet environmental requirements, st offers these de vices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions an d product status are available at: www.st.com . ecopack ? is an st trademark. 13.2 powersso-16 package information figure 23. powersso-16 package dimensions
l99mc6 package and packing information doc id 16523 rev 1 51/55 table 49. powersso-16 mechanical data (1) 1. drawings dimensions include single and matr ix versions. symbol millimeters min. typ. max. a 1.25 - 1.72 a1 0.00 - 0.10 a2 1.10 - 1.62 b 0.18 - 0.36 c 0.19 - 0.25 d (2) 2. dimensions d does not include mold flash protrusion s or gate burrs. mold flash protrusions or gate burrs shal l not exceed 0.15 mm in total (both side). 4.80 - 5.00 e 3.80 - 4.00 e-0.50- h 5.80 - 6.20 h 0.25 - 0.50 l 0.40 - 1.27 k0d-8d x 1.90 - 2.50 y 3.60 - 4.20 ddd - 0.10
package and packing information l99mc6 52/55 doc id 16523 rev 1 13.3 packing information figure 24. powersso-16 tube shipment (no suffix) figure 25. powersso-16 tape and reel shipment (suffix ?tr?) all dimensions are in mm. base q.ty 100 bulk q.ty 2000 tube length ( 0.5) 532 a 1.85 b 6.75 c ( 0.1) 0.6 a c b base q.ty 2500 bulk q.ty 2500 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 12.4 n (min) 60 t (max) 18.4 reel dimensions tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 12 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.05) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.1) 5.5 compartment depth k (max) 4.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed
l99mc6 acronyms doc id 16523 rev 1 53/55 appendix a acronyms table 50. acronyms acronym name csn chip select not ctrl control register por power-on reset sck serial clock sdi serial data input sdo serial data output spi serial peripheral interface sr slew rate stat status register
revision history l99mc6 54/55 doc id 16523 rev 1 revision history table 51. document revision history date revision changes 18-nov-2009 1 initial release.
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